Verification of True Jitter Performance of Clocks in High-Speed Digital Design
Due to the high sensitivity to phase noise, a phase noise analyzer is suitable as a measuring instrument.
Verification of True Jitter Performance of Clocks in High-Speed Digital Design The "R&S FSWP" provides the necessary features for testing low-jitter clocks in both SSC OFF and SSC ON modes. In addition to very high AM suppression in phase noise measurements, it offers excellent phase noise sensitivity required for accurate jitter measurements in low-jitter clocks for high-speed digital designs. 【Electronic Measurement Solutions】 ■ Measurement of phase noise ■ Weighted phase noise based on the corresponding system transfer function ■ Integration of weighted phase noise over the defined jitter integration range *For more details, please refer to the PDF document or feel free to contact us.
- 企業：ローデ・シュワルツ・ジャパン
- 価格：Other
